1. Field of the Invention
This invention relates to a semiconductor device substrate and a method of manufacturing a semiconductor device substrate.
2. Description of the Related Art
Field-effect transistors formed on an SOI (Silicon On Insulator) substrate, which can operate at high speed, enable a high-speed logic circuit to be constructed. Recently, there have been strong demands for such semiconductor devices as system LSIs that include both high-speed logic circuits and DRAMs.
When a DRAM is formed on an SOI layer, charges are accumulated in the body region of a memory cell transistor of the DRAM because of the substrate floating effect of the SOI layer, which results in the degradation of the retention due to an unexpected leak in the DRAM or a shift in the threshold voltage or the like of the pair transistor in the sense amplifier circuit.
In order to completely cancel the substrate-floating effect, it is necessary to form a contact region and a lead-out region from the body section of each MOSFET and control the body potential. However, in order to meet above requirement, the cell area and the area of the sense amplifier section are made extremely large, thereby losing the high integration density, which is the best feature of a DRAM.
To overcome this drawback, there is a method of forming a substrate with an SOI region and a non-SOI region (hereinafter, referred to as a partial SOI substrate). The SOI region has a semiconductor layer formed on an insulating layer formed on a semiconductor substrate. The non-SOI region has a single-crystalline layer formed on the semiconductor substrate without an insulating layer between them.
The semiconductor device formed in the non-SOI region is unaffected by the substrate floating effect. Therefore, forming a field-effect transistor in the SOI region and a DRAM in the non-SOI region makes it possible to form a system LSI that includes a high-speed logic circuit and a DRAM unaffected by the substrate floating effect.
A first method of forming a partial SOI substrate is a SIMOX (Separation by Implantation of Oxygen) method (disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-303385 or discussed in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 66 and 67). A second method of forming the partial SOI substrate is a method of bonding a silicon substrate to a silicon substrate on which an insulating film is patterned (Jpn. Pat. Appln. KOKAI Publication No. 8-316431). A third method of forming the partial SOI substrate is a method of etching partially the SOI layer and insulating layer of an SOI substrate (hereinafter, also referred to as a BOX (Buried Oxide) layer) to remove them (Jpn. Pat. Appln. KOKAI Publication No. 7-106434, Jpn. Pat. Appln. KOKAI Publication No. 11-238860, or Jpn. Pat. Appln. KOKAI Publication No. 2000-91534).
In the first method, or the SIMOX method, since oxygen ions are implanted, defects are liable to occur in a crystal of the SOI layer or a crystal in the bulk layer. In the second method, there is a region where silicon substrates are laminated together. Thus, the crystal orientation deviates in the portion where the silicon substrates are laminated, which causes crystal defects. In the third method, there is a step at the boundary between the SOI region and the non-SOI region, which has an adverse effect on subsequent processes. For example, the focus margin decreases in the lithographic process.
On the other hand, in the third method, although a step exists between the SOI region and the non-SOI region, there are fewer crystal defects in the SOI substrate than in the first and second methods. Therefore, the quality in the third method is better than that in the first and second methods.
To flatten a step occurring between the SOI region and the non-SOI region in the third method, there is a method of forming an epitaxial layer on the non-SOI region and polishing the epitaxial layer (Jpn. Pat. Appln. KOKAI Publication No. 2000-243994).
In this third method, however, since the BOX layer is etched by RIE (Reactive Ion Etching) techniques, the silicon substrate under the BOX layer is damaged by plasma, which causes crystal defects.
Accordingly, it is desirable that the BOX layer be selectively removed by wet etching based on chemical reaction using an NH4F solution or the like. However, since the wet etching using the solution is isotropic, the BOX layer is side-etched.
FIGS. 6A and 6B show sectional views of a partial SOI substrate with an SOI region and a non-SOI region obtained by wet-etching a BOX layer 20 by a conventional method. In manufacture, over the main surface of a semiconductor substrate 10, a BOX layer 20, an SOI layer 30, and a mask layer 40 are formed in that order. Then, the mask layer 40 is patterned. Using the patterned mask layer 40, the SOI layer 30 is etched by RIE techniques. Using a solution, the BOX layer 20 is selectively wet-etched.
In the semiconductor substrate 10, the region where the BOX layer 20 and the SOI layer 30 remain is an SOI region 60. The region where the BOX layer 20 and the SOI layer are removed is a non-SOI region 70. It is assumed that the region where one of the BOX layer 20 and the SOI layer 30 remains and the other is removed is a boundary region 80.
In the non-SOI region 70, the semiconductor substrate 10 is exposed. A single-crystalline layer 50 is grown from the surface of the exposed semiconductor substrate 10.
The BOX layer 20 is subjected to wet etching, with the result that the BOX layer 20 is side-etched not only in a substrate direction going toward the semiconductor substrate 10 but also in a lateral direction perpendicular to the direction going toward the surface of the semiconductor substrate 10. As a result, in a pattern where the width of the SOI layer is less than twice the side-etched width, the SOI layer 30 can lift off. In addition, when the single-crystalline layer 50 is grown, a single crystal also grows from the side face of the SOI layer 30. Since the SOI layer 30 is higher in position than the surface of the semiconductor substrate 10, a single crystal from the side face of the SOI layer 30 grows higher than a single crystal from the semiconductor substrate 10. As a result, a bump 55 is formed in or around the boundary region 80 (see FIG. 6A). At the surface of the semiconductor device substrate near the bump 55, a crystal defect takes place. To form a flat semiconductor device substrate, the process of polishing the bump 55 is needed.
Since the mask layer 40 is removed in a later process, if the flat surface of the single-crystalline layer 50 and the surface of the SOI layer 30 are in the same plane, the surface of the substrate is flat. Therefore, in FIG. 6A, the flat surface of the single-crystalline layer 50 and the surface of the SOI layer are drawn so as to be at the same level.
To overcome these problems, there is a method of covering the side face of the SOI layer 30 with a sidewall protective film 90 after the SOI layer 30 is etched. This method reduces the possibility that the SOI layer 30 will lift off.
However, in a case where the sidewall protective film 90 is thinner than the BOX layer 20, when the BOX layer 20 is etched, the back of the SOI layer 30 is exposed. As a result, the single crystal still grows from the back of the SOI layer 30, with the result that a bump 55 is formed in or around the boundary region 80.
On the other hand, forming a sidewall protective film 90 thicker than the BOX layer 20 causes manufacturing costs to increase and makes the process of forming the sidewall protective film 90 complicated, which is not desirable.